Emerging high-voltage ICs are increasingly susceptible to damage resulting from electrical overstress (EOS) and electrostatic discharge (ESD), i.e., sudden unwanted voltage build-up and currents due to electrical charge displacement during IC assembly and system handling or operation. This is, in particular, a limiting factor in the design for reliability for those technologies that combine devices operating at a variety of internal and external interface voltage levels, such as advanced imaging and industrial systems technologies.
Clamp circuits are often used to shunt ESD currents between the power supply rails of the IC and limit voltage spikes, thereby protecting the internal elements from damage. In the absence of excess voltages at the IC input or output, the clamp circuits should not affect operation of the full IC system. Thus, the current flow through the clamp device is close to zero at voltages up to a trigger voltage level at which current conduction occurs, which should be significantly above the operating voltage of the IC, but below a predetermined voltage level where relatively small internal circuit devices can suffer damage due to the over-voltage condition. Once the trigger voltage is reached, the clamp becomes conductive. In some clamp devices, the voltage between the terminals of the clamp structure then drops to a holding voltage below the trigger voltage, in which condition the device is able to discharge a larger amount of current and dissipate a relatively low power per unit area. Following this current-voltage “snapback,” the clamp device typically conducts a high transient current between its terminals, and if the current conduction condition is not destructive, the leak current at the lower operating voltage stays in the nano-Ampere regime after the overvoltage stress condition has passed.
Many clamp circuits implemented as metal-oxide-semiconductor (MOS) structures are variations of standard low-voltage or high-voltage MOSFET structures. In particular, for high-voltage applications, high-voltage double-diffused (vertical) metal-oxide semiconductor (DDMOS) or planar extended-drain MOS devices may be used. These MOS structures, which are able to operate at relatively large voltages, are themselves very sensitive to ESD-induced damage because they conduct currents largely near the surface, and exhibit limited bulk conduction (i.e., current conduction in deeper regions of the substrate). Failing devices typically develop a large electric field close to the high-voltage MOS junction breakdown voltage (i.e., the trigger voltage), followed by soft failure after a first snapback, and final permanent damage after a second snapback. Soft failure is typically characterized by an initial increase in the leakage current of the device, which poses reliability problems over time and degrades the power efficiency of the system. After a soft-failure, the device is still functional, but elevated leakage currents are more likely obtained under subsequent stress conditions, which may result in permanent device damage. This intrinsic sensitivity to ESD stress renders it difficult to meet customer- and industry-standard reliability requirements in IC applications using conventional high-voltage MOS technologies, and to enable more extensive and advanced circuit functionality on the same chip.
These technology challenges may be addressed by stacking multiple low-voltage devices to implement a higher-voltage ESD switch. However, the feasibility of this approach depends on the ability to isolate the low-voltage devices from the substrate, and to allocate large area for the high-voltage input-output (IO) terminals and the clamp implementation. Due to cost and manufacturing considerations, isolating the devices to realize high-voltage clamping is not practicable in a number of high-voltage mixed-signal developments. In high-voltage technologies where buried layer or deep-well isolation cannot be used in the implementation of the clamp, it is not feasible to stack devices because the high-voltage and low-voltage devices share a common substrate, and the low-voltage devices cannot be connected directly to a high-voltage input or output terminal. Further, isolating layers form reverse-biased junctions with the semiconductor substrate during normal circuit operation and—due to the large area of the junction—can result in significant leakage buildup. Leak current injection, in turn, degrades the energy efficiency of the IC system.
An alternative solution involves large high-voltage planar MOS designed to self-protect during a high ESD transient over-voltage. This large-foot-print approach may be practical for output drivers that need to handle high current levels and meet predetermined on-state resistance and switching speed requirements. However, many emerging output driver circuits include relatively small HV-MOS devices, and, thus, are not self-protected. Over-sizing the device is often not possible due to circuit functionality, energy efficiency, packaging, cost, and silicon-area constraints. Further, high-voltage power-supply clamps that include large high-voltage planar MOS also provide a large capacitance and may be sensitive to false activation by fast voltage changes.
Voltage clamps are typically located at the periphery of an IC, adjacent and connected to the bond pads, which connect the IC, via wires to the pins of the IC package; the pins, in turn, connect to other components of the system in which the IC is utilized. While ICs have undergone significant decreases in feature sizes, the ESD pulses that they need to withstand have remained the same. Consequently, although the density of other circuits has increased, the chip area required to dissipate the ESD pulse has remained nearly constant. In addition, the number of bond pads on a chip has increased with increasing circuit complexity. These trends have resulted in bond pads and ESD protection circuitry occupying a significant proportion (e.g., 10-15%) of the total chip area on many ICs. To reduce the required chip area, bond pads with integrated ESD protection circuitry have been proposed for low-voltage applications. These integrated designs are, however, not readily applicable to high-voltage conditions because the fundamental circuit architectures and associated signal processing applications, as well as the characteristics of power rails and the distribution of pads around the periphery of the chip, generally differ between low-voltage and high-voltage circuits, and further between single-voltage (e.g., digital) and mixed-signal high-voltage circuits. For example, certain features of standard low-voltage structures, such as a common low-voltage bus shared between the power and input/output terminals of the ICs and pull-up/pull-down ESD-robust MOS protection pad drivers cannot be used in or connected to high-voltage designs.
A new approach is desirable to address ESD-related layout, manufacturing, and reliability problems associated with high-voltage ICs (particularly, with large integrated Systems-on-Chip (SoC)) in various advanced automotive, medical, industrial, and consumer applications. The high-voltage pads with integrated over-voltage protection preferably consume a minimum area of the pad ring, yet combine mixed-signal interfaces, multiple voltage levels, and variable power-low and power-high reference voltages. The different reference voltages often pose constraints on the layout of the power rails, which have implications for the overall product reliability. Minimizing the resistance of the power rails around the integrated circuit becomes a problem when the rails are interrupted to connect to integrate a pad connected to a high-voltage signal. With increasing functionality and modularity of the ICs, overcoming the limitations of existing approaches to over-voltage clamping in mixed-signal high-voltage applications becomes increasingly important.
Accordingly, there is a need for effective, small-footprint over-voltage clamp structures for high-voltage MOS applications, which are preferably seamlessly integrated into high-voltage bond pads and form a fundamental part of the mixed-signal integrated circuit pad ring.